AI-Native Robotics Processor
The first purpose-built SoC for embodied AI — RISC-V real-time cores, a hardware LETKF sensor-fusion engine, and an on-chip NPU fused on a single TSMC 28nm die. Replaces the discrete MCU + GPU + FPGA stack in humanoid robots, autonomous drones, and collaborative arms with one chip at under 4 W.
17 mm² of co-designed silicon.
Block-level floorplan on TSMC 28nm HPC+ LVT, FCBGA-400. NoC backbone unifies the NPU, LETKF engine, and four lockstep RT cores around a shared 4 MB SRAM with hardware-arbitrated access.
Everything a robot brain needs. Nothing it doesn't.
Six co-designed subsystems share a 4 MB on-die SRAM fabric with hardware-arbitrated access, eliminating the bus contention that makes discrete multi-chip robot stacks unpredictable.
On-chip NPU
- Systolic INT8/FP16 matrix engine
- Hardware paged attention (2-cycle TLB hit)
- Sparse activation skip — 3× eff. TOPS
- ONNX/TFLite runtime, MLIR compiler
Hardware LETKF Engine
- Local Ensemble Transform Kalman Filter in silicon
- Fuses IMU · pressure · optical flow in < 80 µs
- State-vector width 64 (configurable)
- Direct path to actuator DMA — zero-copy control loop
Sensor Fabric
- Native OC-IMU-001 · OC-ACC-001 · OC-PRS-001 bus
- Hardware timestamping — 10 ns resolution
- Sensor DMA with zero-latency ring buffers
- Auto-calibration co-processor (OC-TBIAS-001 aware)
Real-Time Subsystem
- 4× lockstep RISC-V cores @ 200 MHz
- Hardware task scheduler (no OS jitter)
- Deterministic CAN-FD for joint bus control
- ISO 26262 ASIL-B functional safety path
Memory Hierarchy
- L1: 32 KB I$ + 32 KB D$ per RT core
- L2: 512 KB shared (4-way set assoc.)
- On-die SRAM: 4 MB (sensor scratchpad + model)
- LPDDR4X interface up to 68 GB/s
Security & Safety
- TrustZone-equivalent secure enclave
- Hardware RNG + AES-256 + SHA-3 accelerators
- ECC SRAM + lockstep error detection
- Signed firmware boot chain
DragonX RXP-1 — Key Parameters
Versus today's discrete robot stack
Analytical model. Silicon characterisation in progress on TSMC 28nm.
Versus the chips robotics teams actually buy today.
We do not compete on raw TOPS — Jetson Orin AGX wins that fight 23 ×. We compete on the metrics that determine whether a robot's control loop closes in time: sensor-fusion latency, real-time determinism, sensor I/O depth, and watts. Honest table below.
| Metric | RXP-1 | NVIDIA Jetson Orin AGX | Qualcomm RB6 | Renesas RZ/V2H | NXP i.MX 8M Plus |
|---|---|---|---|---|---|
| AI Peak (INT8 TOPS) | 12 | 275 (sparse) | 15 | 80 | 2.3 |
| TDP (full system) | < 4 W | 15–60 W | 5–15 W | 12 W | 5 W |
| Sensor-fusion latency | < 80 µs (HW LETKF) | 2–5 ms (SW) | 3–8 ms (SW) | 1–3 ms (SW) | 5–10 ms (SW) |
| Real-time cores | 4× lockstep RV64 | — (A78AE only) | — (Kryo only) | 2× Cortex-R52 | 1× Cortex-M7 |
| Native CAN-FD | 2× on-die | via ext PHY | ✗ | 2× | 1× |
| Functional safety | ASIL-B path | ASIL-D (Drive variant) | ✗ | ASIL-D | ASIL-B |
| AI / ML ecosystem | ONNX · TFLite · MLIR | CUDA · TensorRT (vast) | SNPE · TFLite | DRP-AI compiler | eIQ · TFLite |
| Process node | TSMC 28 nm | Samsung 8 nm | TSMC 4 nm | TSMC 16 nm | TSMC 14 nm |
| Unit price (rough) | ~$45 target | $1,999 module | ~$200 SoC | ~$80 | ~$40 |
| India local-content / TPCR | ✓ eligible | ✗ | ✗ | ✗ | ✗ |
| Status (mid-2026) | Place+CTS done · routing WIP | Mass production | Mass production | Mass production | Mass production |
Competitor specs from public datasheets & product briefs (NVIDIA Jetson Orin AGX 64 GB module, Qualcomm RB6 dev platform, Renesas RZ/V2H, NXP i.MX 8M Plus). RXP-1 numbers are pre-silicon design targets — characterised values follow first tape-out.
Where we win
- • Sensor-fusion latency — 25–60× lower than any SW solution
- • Real-time determinism — only RZ/V2H comes close
- • TDP at full system load — fits a 5000 mAh LiPo
- • Native sensor bus — no glue ICs, no level shifters
- • Made-in-India / TPCR-eligible
Where we lose (honest)
- • Raw TOPS — Orin is 23× ahead on peak inference
- • No CUDA / TensorRT — ONNX + MLIR only
- • Older node (28 nm vs Orin 8 nm, RB6 4 nm)
- • No on-die GPU for graphics / vision
- • Zero shipped silicon yet — they are in mass production
The right framing
RXP-1 is not the chip you replace Jetson with — it's the chip you put next to Jetson to run the real-time control loop. Today's robots use Jetson (perception) + STM32 (control) + FPGA (sensor glue). RXP-1 collapses the last two into one die with better fusion than either could do alone — at 4 W, $45, and ASIL-B.
Built for the machines that will be everywhere.
Humanoid Robots
Full-body proprioception + vision inference on a single SoC. Replaces discrete MCU + GPU + FPGA stack in arms like Figure 02 and Apptronik Apollo.
Autonomous Drones
Sub-100 µs LETKF sensor fusion loop enables aggressive manoeuvering in GPS-denied environments. 4 W TDP fits a 5000 mAh LiPo mission profile.
Industrial Arms & AMRs
CAN-FD joint bus + deterministic RT core replace separate safety PLC + motion controller. ISO 26262 ASIL-B path for collaborative robot cells.
Space & Defence Payloads
TSMC 28nm die shrink + radiation-tolerant layout option (in design). TPCR-eligible as Indian-designed IP. Qualified to MIL-STD-883 screen on request.
Designed to pair with DragonX sensor IPs
RXP-1 speaks the native OC-sensor bus protocol — no translation layer, no latency overhead. One trim-cal toolchain across the entire sensor + processor stack.
Evaluating RXP-1 for your robot platform?
We work with robotics teams on architecture evaluation, design-on-contract sensor integration, and custom IP development. DragonX Systems — Stanford · IIT alumni founding team.
First conversation free — send us a 1-page spec and get a fixed-price design quote within 5 working days.