PMIC IP

Tapeout-ready power management IP for GF180MCU 180nm. Bandgap Reference (BGR), Error Amplifier (OTA), LDO regulator, Buck converter, UVLO, and SAR ADC. Full DRC/LVS sign-off with 3σ Monte Carlo and PVT corner qualification. 5×5mm die assembly with sealring and density fill.

Overview

IP Blocks

  • Bandgap Reference (BGR)
  • Folded-cascode OTA
  • LDO Regulator
  • Buck Converter
  • UVLO & Soft-Start
  • 10-bit SAR ADC

Verification Status

  • DRC/LVS zero mismatch
  • 3σ Monte Carlo qualified
  • 45 PVT corners passed
  • 5×5mm die assembly