DragonX Blog
Featured Article
Zenith Architect Platform Integration with RTL Architect: Revolutionizing Hardware Design
Discover how the integration of Zenith Architect platform with RTL Architect is revolutionizing hardware design through our platform architect approach. From native Python/PyTorch support to zero-configuration cloud execution, learn how we're eliminating traditional barriers while delivering cycle-accurate modeling and unprecedented performance.
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Intelligent CPU to Accelerator Offloading Detection for System Evaluation
In the rapidly evolving landscape of heterogeneous computing, determining which parts of your workload should be offloaded from CPUs to specialized accelerators is a critical challenge. At DragonX Systems, we've developed sophisticated techniques for automatically detecting offloading opportunities, enabling more accurate system evaluation and performance optimization.
Intelligent Workload Mapping to Hardware Components
Discover our advanced approach to mapping ML workloads onto hardware components with dynamic memory management and fast bottleneck detection. Learn how our ASAP scheduling algorithm with edge-aware prefetching optimizes performance, and how our visualization tools provide insights for hardware design decisions.
Mapping Matrix Operations to Fixed-Size Systolic Arrays
Explore our sophisticated techniques for mapping matrices of various dimensions and convolutional operations to fixed-size systolic arrays. Learn about our tiling strategies, padding optimizations, and specialized data flow patterns that maximize hardware utilization and performance across diverse workloads.
From PyTorch to Silicon: Our Advanced Neural Network Tracing Pipeline
Dive into our sophisticated PyTorch model tracing system that powers DragonX's hardware design tools. Learn how we transform PyTorch's symbolic trace into our custom IR nodes and graphs, handling memory dependencies, performing topological sorting, and accurately modeling the compute and memory requirements that make our hardware evaluations so precise.
Building a Cycle-Accurate GPU Simulator for NVIDIA H100, A100, and B200
Discover how we built our sophisticated cycle-accurate GPU simulator targeting NVIDIA's most powerful data center GPUs. Learn about our microbenchmarking approach, architectural modeling techniques, and how we achieved up to 97% accuracy in performance prediction for complex AI and HPC workloads.
Building a Python to RISC-V Compiler and Simulator: Our Journey
At DragonX Systems, we've developed a powerful Python to RISC-V compiler and simulator that enables rapid architecture evaluation and performance estimation for chip designs. Our multi-layered compilation strategy parses Python code into an AST, analyzes computational patterns, compiles to RISC-V instructions, and provides detailed performance metrics across various technology nodes.
Hardware Synthesis from High-Level Descriptions
Explore our innovative approach to hardware synthesis from high-level descriptions. We've developed a powerful framework that enables designers to express hardware functionality in high-level languages and automatically synthesize efficient RTL implementations, dramatically accelerating the design process.