RTL to GDSII at GPU Speed.
Proprietary GPU-accelerated EDA engine combining parallel logic minimization, electrostatic density placement, and continuous static timing signoff. Delivering 7–10× faster tapeout iterations than single-threaded CPU flows.
Validated RTL-to-Tapeout Velocity
Side-by-side run of an identical Ibex RISC-V SoC tapeout configuration on matched PDK & timing constraints.
Direct GPU-parallel detailed routing vs. single-threaded CPU baseline.
Measured Performance on Ibex Core Workload
Direct runtime comparison between open-source single-thread flows, multi-threaded commercial EDA profiles, and Accelane GPU acceleration.
| Toolchain Flow | Compute Architecture | Logic Synth | Placement & Route | STA Signoff | Total Runtime | Relative Speedup |
|---|---|---|---|---|---|---|
| OpenLane Reference Flow | 1× x86 CPU Thread (Yosys + OpenROAD) | 38.2 min | 102.4 min | 24.1 min | 164.7 min (2h 44m) | 1.0× (Baseline) |
| Commercial Multi-Thread Profile | 8× CPU Cores (Cadence/Synopsys Profile) | 12.5 min | 34.2 min | 8.8 min | 55.5 min | 3.0× |
| Accelane GPU-Native Engine | 1× NVIDIA GPU (CUDA Kernels) | 3.2 min | 11.4 min | 1.8 min | 16.4 min | ~10.0× Validated |
Internal Research Results
- AES standard-cell area
- 25.74%
- Lower than Siemens Aprisa
- AES routed wirelength
- 20.87%
- Shorter than Siemens Aprisa
- JPEG standard-cell area
- 12.02%
- Lower than Siemens Aprisa
- JPEG functional proof
- 4,426
- Sequential states covered
Separate experimental benchmark candidates. These do not constitute a single production-qualified result or complete timing/power signoff.
Commercial comparison details
| Metric | Siemens Aprisa | Accelane | Result |
|---|---|---|---|
| AES cell area | 25,450.6 µm² | 18,900.1 µm² | −25.74% |
| AES routed wirelength | 305,648 µm | 241,858 µm | −20.87% |
| JPEG cell area | 89,208.2 µm² | 78,486.8 µm² | −12.02% |
| JPEG clock-inclusive routing length | 518,668 µm | 499,190 µm | −3.76% |
Compressing 5-Month Tapeout Iterations to 2 Months
Eliminating the latency gap between Design Verification (DV), Physical Design (PD), and Engineering Change Orders (ECO).
GPU-Native Electronic Design Automation Pipeline
Four tightly coupled execution stages running directly on GPU shared memory without file serialization bottlenecks.
Logic Synthesis & Tech Mapping
Parallel Boolean minimization, multi-level logic optimization, and cell mapping across complex PVT variations directly on thousands of CUDA threads.
Analytical Global Placement
Electrostatic charge-density modeling treats standard cells as charged particles, driving placement convergence at 100M+ gate capacity with zero timing distortion.
Parallel Detailed Routing
Batched routing kernels solve tens of thousands of nets simultaneously across multiple metal layers with dynamic collision negotiation.
Signoff STA & Autonomous ECO
Instantaneous graph-based timing signoff with auto-healing ECO generators that rank buffer insertions and wire spacing patches without manual script intervention.
Accelerate Your Next Tapeout Cycle
Run Accelane against your existing reference benchmark on TSMC 28nm or target advanced nodes. Contact our engineering team for a technical correlation study.